Signals arriving at a receiver are typically corrupted by intersymbol interference (ISI), crosstalk, echo, and other noise. Thus, receivers must jointly equalize the channel, to compensate for such intersymbol interference (ISI) and other distortions, and decode the encoded signals at increasingly high clock rates. Decision-feedback equalization (DFE) is a widely-used technique for removing intersymbol interference where noise enhancement caused by a linear feed-forward equalizer (FFE) may introduce performance problems. For a detailed discussion of decision feedback equalizers (DFEs), see, for example, R. Gitlin et al., Digital Communication Principles, (Plenum Press 1992) and E. A. Lee and D. G. Messerschmitt, Digital Communications, (Kluwer Academic Press, 1988), each incorporated by reference herein. Generally, decision-feedback equalization utilizes a nonlinear equalizer to equalize the channel using a feedback loop based on previously decided symbols. Since DFE techniques are nonlinear, the DFE process does not enhance the channel noise.
In many high-speed applications, such as Fast Ethernet 100BASE-TX, mass storage, Gigabit Ethernet, or Synchronous Optical Networks (SONET), the symbol rates are high. For example, the Fast Ethernet 100BASE-TX standard uses a clock rate of 125 MHz. Thus, the equalization and decoding computations performed by the DFE must be performed at a clock period of 8 nanoseconds. Other advanced data networking applications, such as the SONET standard, may require even shorter clock periods. In many cases, such a short clock period makes the implementation of a DFE challenging or infeasible and forms the critical path in their implementation.
A number of methods have been proposed or suggested for speeding up the DFE processing. For example, K. Parhi, "Pipelining in Algorithm with Quantizer Loops". IEEE Transactions on Circuits and Systems, Vol. 38, No. 7, 745-54 (July 1991), incorporated by reference herein, proposes a look-ahead architecture. Generally, a look-ahead DFE implementation transforms the original DFE feedback loop into a look-ahead structure (with duplicate DFEs for each possible value) and a simple loop with only a large selection multiplexor and one memory device. The look-ahead technique precomputes the symbol value for each possible variation, then utilizes the multiplexor to select the appropriate symbol when the actual value is determined. The complexity of the look-ahead implementation is M.sup.L, where M is the size of symbol alphabet, and L is the number of coefficient taps in the DFE. The speed of the look-ahead method is limited by a select-and-latch operation in the transformed simple loop.
Block (parallel) processing techniques have also been proposed for speeding up adaptive filters for high-speed communication applications. For a discussion of block processing techniques, see, for example, G. A. Clark et al., "Block Implementation of Adaptive Digital Filters", Trans. on ASSP, Vol. ASSP-29, No. 3, (June 1981), incorporated by reference herein. Generally, block processing increases the throughput of the system by processing several inputs (made available through proper buffering) in one clock cycle using duplicated hardware. In return, the clock speed can be set at a lower and more feasible speed. For example, if ten inputs are processed in the same clock cycle, the processing clock speed can be lowered to ten percent (10%) of the clock speed of the received signal, while maintaining the same throughput.
While block processing techniques effectively reduce the required processing speed for general adaptive filter applications, block processing cannot easily be directly used with DFEs because of an output dependency in the feedback loop of DFEs. In the feedback loop of a DFE, each output depends on previous output values that may not be available from the previous cycle. As apparent from the above-described deficiencies with conventional DFEs, a need exists for a technique that reduces the output dependency and further speeds up DFE processing. U.S. patent application Ser. No. 09/206,527, filed Dec. 7, 1998, entitled "A Parallel Processing Decision-Feedback Equalizer (DFE)," assigned to the assignee of the present invention and incorporated by reference herein (hereinafter referred to as "the Azadet 7-4 System"), discloses a parallel implementation of a DFE that speeds up DFE processing. While the Azadet 7-4 System employs look-ahead techniques in each of a plurality of parallel blocks to achieve performance gains, the output dependencies in the disclosed parallel DFE nonetheless produce a delay on the order of N, where N is the number of blocks.